Most computing systems depend upon a reliable clock signal to ensure that processing is synchronized. Processors, data input/output devices, memory, and many other devices use clock signals for synchronization. Without a clock signal, processing may be greatly hindered.
When data is transmitted between computers, it is typically desirable to know the clock signal associated with the data. Unfortunately, this clock signal is not always known. Often the clock signal is not sent with the data because it is not desirable to use valuable bandwidth to send the clock. When the clock signal is not transmitted, it is often desirable to know the clock characteristics, such as unit interval and phase, in order to accurately interpret the transmitted data. Furthermore, even if the clock signal is sent, it may become corrupted or the data may not be fully synchronized to the clock. Such occurrences often happen when the clock signal is distorted by noise.
Even when a clock is not distorted by noise, the source clock may not be in phase with the clock on the receiving side of a transmission. When the source clock and receiving clock are out of phase, data may not be correctly interpreted and receipt errors may occur. Further, the more out of phase the clocks are, the greater affect data jitter may have on data reception. Data jitter is a common challenge for data exchange. Data jitter occurs when data is not triggered at precisely the correct moment. If data jitter is too great, data may be received in a different clock cycle, or unit interval, from that in which it was transmitted. If the receiving clock is out of phase from the source clock, and hence the receiving clock edge may occur late in the source clock cycle, this problem may be exacerbated as smaller amounts of data jitter will push the data into the next clock cycle. If the source and destination clocks are closely aligned, a transmission system may handle clock jitter that distorts the data by almost an entire clock cycle and still accurately decode the data. In an exemplary embodiment of the present invention, the destination clock may have a clock edge at a time equivalent to the middle point of the source clock edge. Using such an arrangement, the system 200 may correctly interpret data that occurs up to one half unit interval early or one half unit interval late for a total jitter tolerance of one unit interval. Alternatively, the virtual clock may be aligned with the source clock such that the clock edges occur at substantially identical times. In such an embodiment, the system 200 may not correctly interpret data that arrives early, but may interpret input data that arrives close to one full unit interval after the clock edge. Specific system requirements or data characteristics may prompt the system 200 to be configured for a specific correlation between the source clock edge and the destination clock edge.
If a source clock does not transmit data at precisely the desired clock speed, the destination clock may not be sufficiently synchronized because the destination clock may be set to clock data in at a specific rate. The destination clock may operate correctly for a time, and slowly move out of phase until significant errors occur. After a period of reception errors, the destination clock may move into closer alignment with the source clock to correctly receive data for another period of time. If both clocks are in phase and operate at the same rate, this problem may be greatly reduced.